It is known that, with respect to CMOS technology, lower temperatures cause an IC chip to operate at a higher frequency because of increased carrier mobility. To that end, thermo-electric cooling methods have been used to improve CMOS IC chip operating speed, where an increase is desired. (See U.S. patent application Ser. No. 457,641, having NCR Docket Number 4432, and titled METHOD AND APPARATUS FOR LOW TEMPERATURE INTEGRATED CIRCUIT CHIP TESTING AND OPERATION, and filed concurrently with the present application, which application is also assigned to the assignee of the present patent application, and hereby expressly incorporated by reference.) The aforementioned patent application teaches that cooling can be used to increase the operating speed of an existing CMOS IC chip, in order to simulate the operation of a faster, but yet unavailable IC chip.
In addition to using liquid cooling for chip testing and simulation purposes, liquid cooling methods can be used to increase the operating speed of actual CMOS IC chips during normal operation. Liquid cooling methods can also be used to simply withdraw excess heat generated by the circuits in high-throughput IC chips.
In contrast to CMOS circuits, emitter-coupled logic (ECL) circuits increase their operating speed with an increase in operating temperature. However, excessive temperatures (greater than approximately 85 degrees Celsius) can cause burnout of an ECL circuit. Therefore, ECL circuits must be properly cooled to maintain a satisfactory mean time between failure.
A problem in prior art thermo-electric cooling methods is that cooling liquid often leaks onto unintended components during normal operation, mostly caused by the cooling liquid being pumped into the cooling region surrounding the targeted IC chip, and seeping through cooling region crevices.